The present invention relates to a voltage detection circuit for detecting the output voltage of a voltage generation circuit mounted on a semiconductor device, a semiconductor device, and a method for controlling the voltage detection circuit.
There is a type of semiconductor device including a voltage generation circuit for generating an internal voltage differing from a power supply voltage supplied from an external device. A voltage detection circuit for detecting the output voltage of the voltage generation circuit is arranged on such a semiconductor device. More specifically, in the voltage detection circuit, division voltage, which corresponds to the output voltage of the voltage generation circuit, is compared with a reference voltage to detect whether the output voltage has reached a target voltage level based on the comparison result. A typical voltage detection circuit has a voltage dividing resistor, which functions as a device for generating the division voltage. However, current constantly flows through the voltage dividing resistor. Thus, for a semiconductor device requiring low power consumption (e.g., non-volatile memory), the voltage detection circuit uses a capacitor in place of the voltage dividing resistor. In such a voltage detection circuit, voltage must be accurately detected from the capacitance ratio.
FIG. 13 shows a conventional voltage detection circuit 31, and FIG. 14 shows an operation waveform chart of the voltage detection circuit 31.
The voltage detection circuit 31 is a circuit for detecting the output voltage VPP of a voltage generation circuit 32 and controls the voltage VPP so that it becomes equal to a target voltage value. The voltage detection circuit 31 includes two series-connected capacitors C1 and C2, a comparator 21, and an NMOS transistor Tn1.
The capacitors C1 and C2 divide the output voltage VPP of the voltage generation circuit 32. The division voltage div of the capacitors C1 and C2 (voltage at node N1 between the capacitors C1 and C2) is supplied to a non-inverting input terminal of the comparator 21, and a reference voltage Vref (e.g., 1.3 V) is supplied to an inverting input terminal of the comparator 21.
The drain of the NMOS transistor Tn1 is connected to the node N1 of the capacitors C1 and C2, and the source of the transistor Tn1 is connected to the ground GND. Further, a reset signal RST is provided to the gate of the NMOS transistor Tn1.
Referring to FIG. 14, when the voltage detection circuit 31 starts voltage detection, the NMOS transistor Tn1 is activated by the reset signal RST having a high level, and the division voltage div of the capacitors C1 and C2 is initialized to ground potential (0 V). At time t1, the reset signal RST is inverted to a low level and the transistor Tn1 is inactivated. Thus, the node N1 of the capacitors C1 and C2 enters a floating state. After time t1, the division voltage div of the capacitors C1 and C2 changes in accordance with the output voltage VPP. That is, when the output voltage VPP increases by the boosting operation of the voltage generation circuit 32, the division voltage div also increases at a changing degree that is in accordance with the capacitance ratio of the capacitors C1 and C2.
The comparator 21 compares the division voltage div and the reference voltage Vref, and outputs an output signal COM having a voltage level that is in accordance with the comparison result. That is, the comparator 21 outputs the output signal COM at a low level when the division voltage div is lower than the reference voltage Vref. Further, the comparator 21 outputs the output signal COM at a high level when the division voltage div is greater than or equal to the reference voltage Vref. The output voltage of the voltage generation circuit 32 is controlled, based on the output signal COM, so that it becomes equal to the target voltage value.
The voltage detection circuit performing voltage detection based on the capacitance ratio is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2002-51538.
In a non-volatile semiconductor memory device, the writing and erasing of data is carried out utilizing semiconductor characteristics, such as the break down characteristic and the tunneling characteristic. More specifically, in a non-volatile memory, the voltage generation circuit generates voltage (e.g., 10 V), which is higher than the power supply voltage (e.g., 3 V), or negative voltage (e.g., −10 V). The voltage generation circuit then applies the high voltage or negative voltage to a word line to write or erase data.
In a non-volatile memory, a voltage detection circuit 31 shown in FIG. 13 is used to control the output voltage of the voltage generation circuit at a predetermined voltage (high voltage=10 V, negative voltage=−10 V). The voltage detection circuit 31 performs voltage detection based on the capacitance ratio. Thus, the voltage detection circuit 31 consumes less power than a voltage detection circuit that performs voltage detection based on the resistance ratio.
However, tailing current (referred to as sub-threshold current or off leak current) flows through the NMOS transistor Tn1, which initializes the division voltage div in the voltage detection circuit 31. This fluctuates the output voltage VPP.
More specifically, when the output voltage VPP of the voltage generation circuit 32 reaches the target voltage value, the division voltage div of the voltage detection circuit 31 becomes equal to the reference voltage Vref (1.3 V). In this state, the transistor Tn1 is inactivated by the reset signal RST having a low level. However, the division voltage div, which is equal to the reference voltage Vref, is applied between the source and drain. Thus, there is a flow of a slight leak current. In this manner, when off leak current flows through the transistor Tn1, the division voltage div becomes lower than the reference voltage Vref. In this case, the voltage generation circuit 32 continues the boosting operation regardless even though the output voltage VPP has reached the target voltage value. Thus, the output voltage VPP becomes higher than necessary.
Such a phenomenon is not problematic as long as the operation time for voltage detection with the voltage detection circuit 31 is relatively short with respect to the decrease in the output voltage VPP caused by the off leak current. However, the write operation or the erase operation of data in the non-volatile memory requires time (several tens of milliseconds) that is several thousand times longer than the read operation time (several tens of nanoseconds). Thus, in a semiconductor device requiring a long period of time for the voltage detection operation as in the non-volatile memory, the output voltage VPP of the voltage generation circuit 32 becomes higher than necessary due to the off leak current of the transistor Tn1.
It is an object of the present invention to provide a voltage detection circuit, a semiconductor device, and a method for controlling the voltage detection circuit that suppresses voltage fluctuation caused by off leak current of a transistor to accurately perform voltage detection.